1. Field of the Invention
The present invention relates to an input/output circuit and an input/output device, which in particular are capable of impressing into an output terminal an external power supply voltage which is higher than an operation voltage, and have a tolerant function which pulls an output potential up to the level of the external power supply voltage.
2. Description of the Background Art
In recent years, as semiconductor integrated circuits have turned to require less power, technology which makes the semiconductor integrated circuits require less voltage is being pursued. However, in connecting different semiconductor integrated circuits which operate with different power supply voltage (i.e. with different signal level), the semiconductor integrated circuit operating with the lower power supply voltage may not be able to endure the influence of the semiconductor integrated circuit operating with the higher power supply voltage, as a result of which the semiconductor integrated circuit operating with the lower power supply voltage may be damaged. For example, if a semiconductor integrated circuit which operates with a power supply voltage of 3.3 V (hereinafter referred to as 3V system semiconductor integrated circuit) and a semiconductor integrated circuit which operates with a power supply voltage of 5 V (hereinafter referred to as 5V system semiconductor integrated circuit) are connected, the 3V system semiconductor integrated circuit may be damaged by the influence of the 5V system semiconductor integrated circuit.
In order to cope with such problem, in the conventional art, it has been common for an input/output circuit which is capable of impressing an external power supply voltage that is higher than an internal power supply voltage, or an input/output circuit which is capable of pulling the power supply voltage up to the level of the external power supply voltage that is higher than the internal power supply voltage, to be used as a signal interface with respect to a semiconductor integrated circuit on the lower voltage side.
Such input/output circuit is disclosed in Japanese Laid Open Patent Application No. 9-139087 (hereinafter to be referred to as patent reference 1) and Japanese Laid Open Patent Application No. 2002-280892 (hereinafter to be referred to as patent reference 2), for instance. In a prior art input/output circuit as introduced by the patent references 1 and 2, a first p-channel MOS (metal oxide semiconductor) transistor (hereinafter to be referred to as P-MOS transistor) for pull-up and a first n-channel MOS transistor (hereinafter to be referred to as N-MOS transistor) for pull-down are connected in series, and to this connecting part, an output pad is connected. Between the gate of the first P-MOS transistor and the output pad, a switch of a second P-MOS transistor is connected. On the other hand between the drain of the first N-MOS transistor and the output pad, a second N-MOS transistor for reducing a voltage impressed between the source and drain of the first N-MOS transistor is connected.
In this structure, when an external voltage which is higher than an internal power supply voltage is impressed to the output pad, for instance, the second P-MOS transistor will be turned on. Through this operation, the second P-MOS transistor will function as an output transistor. At this time, the first P-MOS transistor will be turned off as the gate potential of the first P-MOS transistor becomes the external voltage, and therefore, current flow from the output pad toward the side of the internal power supply voltage can be prevented. In addition, even when a voltage surpassing a withstand pressure of the first N-MOS transistor is impressed to the output pad, it is possible to prevent the first N-MOS transistor from being damaged by the voltage impressed to the output pad because the voltage impressed between the source and drain of the first N-MOS transistor is being reduced by the second N-MOS transistor.
In the prior art input/output circuit as described above, when the external voltage which is higher than the internal power supply voltage is impressed, current will flow into a node connected to the gate of the first P-MOS transistor via the second P-MOS transistor having the internal power supply voltage being impressed to its gate. Due to such operation, this node, i.e. the gate of the first P-MOS transistor, will be pulled up to the level of the external voltage and the first P-MOS transistor will be turned off. Thereby, a current path from the output pad to the side of the internal power supply voltage will be shut off.
In such structure, however, if, for instance, in a normal operation, an external power supply voltage surpassing the internal power supply voltage is impressed to the output pad while the first P-MOS transistor is being turned on, it takes a while until the first P-MOS transistor turned off. In other words, the first P-MOS transistor will continue to be turned on until the gate potential of the first P-MOS transistor is pulled up to the level of the external power supply voltage, which results in having components which charge the gate of the first P-MOS transistor and components which flow into the side of the internal power supply voltage via the first P-MOS transistor incorporated in the current from the external power supply voltage. Therefore, it will take time to have the gate potential of the first P-MOS transistor pulled up by the time the first P-MOS transistor is turned off (i.e. steps will occur in the pull-up waveform), which leads to a problem of increasing power consumption.
In view of the above, it will be apparent to those skilled in the art from this disclosure that there exists a need for an improved input/output circuit and an improved input/output device. This invention addresses this need in the art as well as other needs, which will become apparent to those skilled in the art from this disclosure.